The present invention relates to testing of a plurality of integrated circuit (IC) elements. In particular, embodiments of the invention include methods and systems used to identify stresses or alterations in physical structure or function below IC element failure states, conditions, or points.
One type of IC includes NAND Flash which is a memory technology that is used in a wide variety of systems, including many systems with radiation hardness requirements. Characterization of radiation hardness of NAND Flash bit cells can include measurements of failure of the bit cells to retain data in various radiation environments. To better understand and predict the behavior of these devices, it would be useful to be able to measure changes in bit cell parameters caused by radiation exposure or other stresses below a threshold at which a bit cell failure occurs outside of a factory setting with specific knowledge of manufacturing test modes. Direct measurement of, for instance, bit cell threshold voltages without various types of such manufacturer information is not possible as manufacturers deliberately obscure these details in the construction of the digital interface to their devices. Careful characterization of parts then requires the measurement of large numbers of bits through the digital interface to obtain statistically significant results.
Despite limitations posed by manufacturers, some limited device specific success has been achieved in recovering details of analog characteristics of bit cells. However, such device specific approaches are not helpful given some devices do not implement features relied upon and, in many of the devices that do, necessary modifications to such device specific operation modes are undocumented thereby making interpretation of resulted challenging or impossible. Some types of modifications to original equipment manufacturer (OEM) IC operations have been attempted for purposes such as programming an IC to shield information for data security objectives. However, data or device security teams have a different focus and expertise mix than device characterization or fault analysis groups with different journals and publications that are generally not of interest of use to each other. Existing efforts with data security objectives would not function or be usable in device characterization for fault or condition detection purposes given a core operation of the data security action, e.g., issuing a reset command during a write operation, would not yield any useful information for device characterization. Even assuming a device characterization expert would show any interest in data security activities, a desire to engage in pure or basic research to determine of data security applications might have some application to device characterization would be required without any significant probability that results from one field might be improved or modified for use in another. Significant additional inventive effort would be required even assuming such an effort might actually produce a new method or apparatus. For example, additional operations would be needed beyond a data security operation along with creation of an analytical framework directed towards device characterization to detect specific conditions or changes in an IC under test which would require testing and validation to see if such a new approach would even work or produce useful information.
According to an illustrative embodiment of the present disclosure, apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below the thresholds for IC element or bit cell failure.
Additional features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description of the illustrative embodiment exemplifying the best mode of carrying out the invention as presently perceived.